Home » Electronic News » Depth: How is the RISC-V instruction set architecture implemented globally?

Depth: How is the RISC-V instruction set architecture implemented globally?

Posted by: Yoyokuo 2022-05-05 Comments Off on Depth: How is the RISC-V instruction set architecture implemented globally?

The development background of the instruction set architecture, the external environment: (1) In the context of the trade war, it is imperative to be independent and controllable; (2) Policy-driven, the integrated circuit industry ushered in development opportunities; (3) The new generation of information technology accelerates penetration, emerging The field has put forward higher demand for chips. Internal factors: (4) From the perspective of the industry, the mainstream instruction set architecture is complex, the hardware implementation is difficult, the licensing fee is high, and the cost of chip companies remains high.

The development background of the instruction set architecture, the external environment: (1) In the context of the trade war, it is imperative to be independent and controllable; (2) Policy-driven, the integrated circuit industry ushered in development opportunities; (3) The new generation of information technology accelerates penetration, emerging The field has put forward higher demand for chips. Internal factors: (4) From the perspective of the industry, the mainstream instruction set architecture is complex, the hardware implementation is difficult, the licensing fee is high, and the cost of chip companies remains high.

The technical characteristics of RISC-V instruction set architecture: it is concise, modular, extensible and open source. Through the combination and expansion of limited instruction sets, it can build microprocessors suitable for any field.

The RISC-V industry ecology is gradually improving. International industry – Multiple RISC-V open source versions and commercial IPs were born; technology giants and start-ups have been deployed; industrial applications have landed one after another. Domestic industry – Huawei, ZTE and other large enterprises, as well as some small and medium-sized enterprises (such as C-SKY) and maker groups joined the RISC-V Foundation; the first open-source RISC-V processor in China was born – Hummingbird E200 (for It is designed for extremely low power consumption and extremely small area scenarios).

RISC-V meets the new needs of personalized and customized chips. Based on the minimalist, modular and scalable characteristics of RISC-V, it is possible to customize chips with low power consumption, small area, and personalization and differentiation at the same time, and the application of fragmented scenarios (IOT, AI) is promising.

Suggestions for the development of my country’s RISC-V industry: collaboratively build an industrial development environment for the application and promotion of RISC-V technology; collaboratively establish a RISC-V test and evaluation system; establish and improve various security systems to rise to the national strategic level.

Depth: How is the RISC-V instruction set architecture implemented globally?

RISC V connotation analysis

RISC-V is a new, simple, open and free instruction set architecture. It was invented in 2010 by professors Krste Asanovic, Andrew Waterman, and Yunsup Lee of the University of California, Berkeley, and other developers, and it has been widely used in the field of computer architecture. Great support from dean David Patterson; driving factor.

The mainstream instruction set architecture is extremely complex and redundant;
High patent and licensing fees;
Other open source architectures have many problems: OpenRISC is an open source processor core, not an instruction set architecture, and the license is GPL, which means that all instruction set changes must be open source (RISC V license is BSD License Licensed, open source and commercial); SPARC power consumption area is too expensive, and it is not a strong replacement for x86.

Target:

Become a completely open instruction set that can be freely used by any academic institution or commercial organization.
It has become a standard instruction set that is truly suitable for hardware implementation and is stable.

Depth: How is the RISC-V instruction set architecture implemented globally?

For the smooth promotion of the RISC V architecture, the RISC V Foundation was established in 2015. Responsible for maintaining the standard RISC V instruction set manual and architecture documentation, and promoting the development of the RISC V architecture. At present, the foundation includes 108 member units, including 18 platinum members and 90 ordinary members, and the number of members continues to grow rapidly. Many large and medium-sized enterprise-level scientific research institutions in China have also joined the RISC V Foundation, such as ZTE, Huawei, Hangzhou Zhongtian, and the Institute of Computing Technology, Chinese Academy of Sciences.

RISC-V technical characteristics

Vertical comparison (RISC V vs RISC is compared from three dimensions: pipeline, overall performance of the instruction set, and architectural length. The classic five-stage pipeline of the instruction set includes: instruction fetch, decoding, execution, memory access and write back.

Instruction Fetch Instruction Fetch refers to the process of reading instructions from memory; decoding is the process of translating instructions fetched from memory; the process of performing real operations on instructions; fetching memory access instructions The process of reading from the area, or writing to the memory; writing back the process of writing the result of the execution of the instruction back to the general-purpose register group.

Instruction fetch stage: RISC V improves instruction fetch speed by regularizing and simplifying instruction coding. At the same time, necessary elements are added to the instruction coding, or the instruction function is clearly defined, which reduces the judgment time when fetching instructions, thereby increasing the instruction fetching speed and reducing losses.

Decoding and execution stage: RISC V has regular and concise instruction encoding, which improves the decoding speed and reduces the burden of hardware design. At the same time, relying on the optional compressed instruction subset, RISC V improves the code density, and the execution stage does not need to distinguish the instruction length, which improves the execution efficiency.

Memory access stage: RISC V reduces some performance by simplifying and restricting instructions, but also reduces the difficulty of accessing some hardware implementations.

Depth: How is the RISC-V instruction set architecture implemented globally?

The technical characteristics of RISC-V are simplicity, modularity, extensibility and open source. Through the combination and expansion of a limited instruction set, a microprocessor suitable for any field can be constructed.

Multiple RISC V open source versions and commercial IP were born

Technology The RISC V instruction set architecture has minimalist, open source, and modular technical features. Many commercial companies and startups have joined the RISC V architecture development and design competition, and multiple RISC V open source versions and commercial IP have emerged. Mainly present the following characteristics:

Based on RISC V open source or commercial Core, compared with ARM architecture, it has higher performance, lower power consumption and smaller area, supports multiple configuration interfaces, has strong scalability, and has a higher safety factor.

Most open source processors only provide the implementation of the processor core and do not provide a supporting SoC.

Depth: How is the RISC-V instruction set architecture implemented globally?

Tech giants and startups are lining up

Many technology giants and startups have joined the RISC V competition to get rid of the monopoly of ARM and X86 architectures on mobile and PC. Looking at the global RISC V commercial companies, there are the following characteristics:

1. From the perspective of regional distribution, most companies are concentrated in the United States, Europe and Asia, and the United States is the main one.

2. From the perspective of the original processor architecture, many large technology companies that originally relied on the ARM architecture joined the RISC V competition, mainly due to ARM’s high licensing fees and royalties. In addition, Intel announced to invest in SiFive and actively deploy RISC V.

3. From the perspective of application fields, most applications of RISC V are concentrated in emerging fields, such as the Internet of Things and artificial intelligence.

a) Based on the dominance of Intel and ARM in the server, PC and mobile fields respectively, the software ecology is difficult to shake;

b) The minimalist, scalable, and modular features of RISC V are suitable for the low power consumption, personalization and customization of chips in the fields of IoT and artificial intelligence.

4. From a technical point of view, the embedded control core based on the RISC V architecture has been widely used in the industry, and gradually entered the top-level chip of the device, verifying the security and stability of the RISC V architecture. Such as NVIDIA, Google, CEVA and Codasip.

5. Gradually improve the industrial ecology: With the commercialization of the RISC V architecture, there have been many companies providing IP cores for RISC V tracking solutions (such as UltraSoc), providing embedded analysis functions, greatly reducing chip development costs and improving profitability. .

6. From the perspective of regional distribution, it is still concentrated in the United States; from the perspective of business model, it is mainly based on the development of chips based on RISC V architecture, and only one company, SiFive, develops IP cores; in terms of application areas, it is still concentrated in the fields of Internet of Things and artificial intelligence .

Depth: How is the RISC-V instruction set architecture implemented globally?

Depth: How is the RISC-V instruction set architecture implemented globally?

RISC-V industry applications have landed one after another

With the gradual improvement of the RISC V ecosystem, many industry applications have landed one after another.

Ashling Systems partnered with Imperas Software to provide integrated tools and solutions for RISC V software development;
CEVA Announces Its RivieraWaves Bluetooth and Wi-Fi IP Platform Now Available With Optional Integrated Open Source RISC V MCU
GreenWaves Technologies launches RISC V-based GAP8 IoT application processor;
Trinamic licenses Codasip’s Bk3 RISC V processor for next-generation motion control applications;
Imperas Software’s RISC V-based RV64GC high-performance scalable platform suite that runs Linux fast.

RISC-V Meets New Demands for Personalized and Customized Chips

The current application fields and market positions of mainstream instruction set architecture chips:
In the embedded field, ARM comes out on top. Combining data from research institutions such as Gartner and IDC, ARM estimates that about 34 billion devices used the company’s authorized instruction set chips in 2017, with a total of 41 billion chips. More than 90% of the world’s smartphones and tablets use the ARM-licensed instruction set architecture.

In the PC field, the x86 architecture adopted by companies such as Intel and AMD occupies an absolute dominant position.

Depth: How is the RISC-V instruction set architecture implemented globally?

Based on the minimalist, open source, modular and scalable technical characteristics of RISC V, it has had many impacts on the chip industry:

1. Based on the minimalist, modular and scalable characteristics of RISC V, it is possible to customize chips with low power consumption, small area, and personalization and differentiation at the same time, and the application of fragmented scenarios (IOT, AI) is promising.

2. Open source leads to many participants, and a hundred schools of thought contend in the initial stage. Chips based on RISC V will come in many forms, the good and the bad are serious, and manufacturers with strong design and process technology will benefit (Manuscript: The design involves a series of technologies such as RTL coding, layout, semiconductor process, and packaging, and the test standards are also different).

3. Scalability leads to an increase in the functional richness of RISC V-based chips.

4. Open source RTL code and unpredictable memory access lead to improved chip security.

5. The chip ecological pattern based on the original mainstream architecture is difficult to shake for a while, and emerging fields will have a place. Especially in the field of the Internet of Things, it has a certain substitution effect on the chip of the ARM architecture.

The development of my country’s chip industry is weak, and major intellectual property rights have been controlled by people for a long time. In the face of Sino-US trade friction, it is imperative for my country to develop independent and controllable development, develop independent intellectual property rights, establish my country’s own instruction set architecture standards, build a chip industry ecology, and expand my country’s semiconductor and integrated circuit industries. At present, my country’s chip industry mainly presents the following characteristics:

1. 90% imported: According to estimates by International Business Strategies Inc., nearly 90% of the US$190 billion worth of chips used in China are imported or produced by foreign companies in China.

2. The CPU instruction cluster dominates: It has collected most of the influential instruction sets in the world, including ARM, MIPS, PowerPC, SPARC, RISC V, X86 and other instruction sets. Representative manufacturers: Loongson, Insignia, Huawei HiSilicon, Spreadtrum. The main problems faced: lack of independent intellectual property rights, lack of unified instruction set standards.

The Links:   LM170E03-TLG3 MG15Q6ES42